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Global Descriptor Table
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#	Item
1	1 FROM RING3 TO RING0: EXPLOITING THE XEN X86 INSTRUCTION EMULATOR Andrei Vlad Luțaș Bitdefender Add to Reading List Source URL: labs.bitdefender.com Language: English - Date: 2016-01-22 04:06:36 Computer architecture Computing X86 architecture Interrupts X86 instructions Memory management Interrupt descriptor table Task state segment Global Descriptor Table Interrupt flag X86 Interrupt
2	Datenstrukturen Funktionen GDT (global descriptor table) Add to Reading List Source URL: ohm.hgesser.de Language: English - Date: 2015-01-13 07:42:49 Software engineering Computing Computer programming C Procedural programming languages Data types Primitive types Typedef Struct E Integer ALGOL 68
3	The Page-Fault Weird Machine: Lessons in Instruction-less Computation Julian Bangert, Sergey Bratus, Rebecca Shapiro, Sean W. Smith Abstract not unique to either the x86 Memory Management Unit Add to Reading List Source URL: www.cs.dartmouth.edu Language: English - Date: 2013-09-11 09:08:25 Virtual memory Memory management Central processing unit Task state segment Global Descriptor Table X86 assembly language Protected mode Interrupt descriptor table Memory management unit Computer architecture X86 architecture Interrupts
4	Microsoft Word - HDA016 DCN RO clarification.doc Add to Reading List Source URL: www.crashrecovery.org Language: English - Date: 2012-03-17 07:56:41 IBM PC compatibles X86 architecture Conventional PCI Data structure alignment Direct memory access Word Global Descriptor Table Computer hardware Computing Computer buses
5	GDT and LDT in Windows kernel vulnerability exploitation Matthew “j00ru” Jurczyk and Gynvael Coldwind, Hispasec Abstract Add to Reading List Source URL: vexillium.org Language: English Global Descriptor Table Local Descriptor Table Protected mode X86 memory segmentation Task state segment Call gate Memory protection Segment descriptor Context switch Computer architecture X86 architecture Memory management
6	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: developer.amd.com Language: English - Date: 2013-10-24 18:24:55 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86
7	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: support.amd.com Language: English - Date: 2013-11-01 16:14:30 X86 Interrupt descriptor table Task state segment Global Descriptor Table Protected mode CPUID Processor register Context switch INT Computer architecture X86 architecture Control register
8	AMD64 Architecture Programmer’s Manual, Volume 2: System Programming Add to Reading List Source URL: developer.amd.com Language: English - Date: 2013-10-24 18:25:06 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86
9	PDF Document Add to Reading List Source URL: support.amd.com Language: English - Date: 2013-05-08 17:06:40 Control register Interrupt descriptor table Task state segment CPUID Global Descriptor Table Protected mode Processor register 64-bit Context switch Computer architecture X86 architecture X86
10	PDF Document Add to Reading List Source URL: www.offensivecomputing.net Language: English - Date: 2007-10-30 18:30:44 Memory management X86 architecture VMware Virtual machines Interrupt descriptor table Interrupts Local Descriptor Table Global Descriptor Table Hypervisor System software Software Computer architecture

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